August 25, 2026 · Decision research
Semiconductor Supply Chain
Finding
Yes. Move from passive CONSIDER to targeted ACT/HEDGE, but do not make a single-node packaging bet. The weakest assumption was the ranking claim that one bottleneck explains all accelerator lead times and that front-end capacity is irrelevant. Current primary disclosures instead support a synchronized constraint: TSMC packaging is demonstrably gating customer growth, while HBM, conventional DRAM wafer supply, and test capacity are independently tight.
What changed
The July 2026 supplier disclosures convert the packaging thesis from an industry estimate into an explicit TSMC management statement, while Micron's latest call supplies the missing counterweight: memory supply remains below demand beyond 2027 and depends on new fabs. Advantest also says inference-AI test demand is above its April forecast.
Decision
Act now on secured access to advanced packaging, HBM/DRAM, and test/substrate capacity, using multi-source commitments and cancellation flexibility. Keep leading-edge wafer exposure as optionality, not the primary incremental bet. Treat power as a site-specific gating test, not yet as proof of a semiconductor bottleneck.
Watch next
Reverse the decision if TSMC says packaging no longer limits customer growth, memory suppliers report supply catching demand, or actual accelerator shipments are delayed despite available package and HBM slots. Escalate power only when a named project has a denied or delayed interconnection or firm-power approval.